1. Field of the Invention
The present invention relates generally to logic analyzers that are used to facilitate the design of digital logic devices. More preferably, the present invention relates to an on-chip logic analyzer capable of receiving internal state data of a digital logic device, and of selecting a portion of that internal state data for storage in a historical log. Still, more particularly, the invention relates to a word recognizer for an economical on-chip logic analyzer, which permits filtering of internal state data to select information for storage that is of particular interest during debugging operations.
2. Background of the Invention
The design and development of digital logic circuits has become increasingly complex, due in large measure to the ever-increasing functionality offered in such circuits. Integrated circuits are constantly surpassing milestones in performance, as more and more functionality is packaged into smaller sizes. This enhanced functionality requires that a greater number of transistors be included in an integrated circuit, which in turn requires more rigorous testing requirements to insure reliability once the device is released. Integrated circuit designs are repeatedly tested and debugged during the development phase to minimize the number and severity of errors that may subsequently arise. In addition, chips may be tested to determine the performance characteristics of the device, including the speed or throughput of the chip, software running on the chip, or the aggregate performance of the system.
As integrated circuits become more complex, the length of the increases, requiring a greater lead-time before product release. In addition, as the complexity of integrated circuits increase, it becomes necessary to fabricate more prototype iterations of the silicon (or “spins” of silicon) in order to remove successive layers of bugs from the design, thereby increasing the engineering and material cost of the released product. It would be desirable to reduce these engineering and material costs and speed up the product cycle. Moreover, if the most relevant state data was available for analysis by the debugging team, the debugging phase for products could be reduced significantly, thereby minimizing cost, and enabling an earlier product launch.
One of the chief difficulties encountered during the debug phase of a product is identifying the source of an error, and obtaining relevant data regarding the conditions existing at the time of the error. This can be extremely difficult because the error may make it impossible to obtain state information from the integrated circuit. For example, in a processor, an error may cause the processor to quit executing, thus making it impossible to obtain the state data necessary to identify the source of the error. As a result, the debug process often unfortunately requires that the debug team infer the source of the error by looking at external transactions at the time of the error, instead of being able to look at the internal state data. The normal technique for probing external busses is to solder a wire onto a terminal or trace. Unfortunately, merely adding a soldered wire to a terminal or trace can create signal reflections, which may distort the data being monitored. Thus, the manual probing of bus terminals and traces is impractical and inaccurate, especially those attached to high speed, highly complex chips. More sophisticated techniques are also used, but are expensive and suffer, albeit to a lesser degree, from the same effects. Further, because the state information available on these busses is typically a small subset of the processor's state, the debug team must make guesses regarding the state of data internal to the processor. If the internal state of the processor could be acquired and stored, these inferences would be replaced by solid data. By reducing the designer's uncertainty and increasing the available data, this would be beneficial in solving problems with the processor hardware or software.
In certain products under development, such as new microprocessors under development by the assignee of the present invention, the number of transistors is exceedingly large and their dimensions are exceedingly small. Both of these factors make it practically impossible to probe internal terminals of the chip or internal wire traces. Moreover, to the extent that certain internal terminals and traces could be probed, the conventional methods for conducting such a probing operation are extremely expensive, and some might potentially corrupt the state of the terminals and traces being probed. Consequently, the only common technique currently available to test or probe the state of terminals and traces in highly complex chips is to route signals through the chip's external output terminals, to some external interface. This approach, however, suffers in several respects.
First, as noted above, the signals obtained from the external output terminals are removed from the signal states of the internal terminals and traces. Thus, this technique requires the debugging team to infer the state of the internal terminals and traces from signals appearing on an external bus. Second, routing the desired state to external terminals often requires more wiring, silicon, drivers, pads and power than is affordable. Attempts to do so can compromise the normal functioning of the chip. And costs escalate throughout the design, often impacting the micropackaging and system board as well as the die. Third, oftentimes the internal clock rate of the chip operates at a much higher rate than the external logic analyzers that receive and process the data. As an example, processor designs currently under development operate at clock speeds up to and exceeding 2.0 GHz. The fastest commercial logic analyzers, despite their expense, are incapable of operating at GHz frequencies. Thus, either certain data must be ignored, or some other mechanism must be employed to capture the high-speed data being generated on the chip. The typical approach is to run the chip at a slower clock speed so the data can be captured by external test equipment. This solution, however, makes it more difficult to detect the bugs and errors that occur when the chip is running at full clock speeds. Some errors that occur at full clock speed will not be detected when the clock speed if reduced to accommodate the off-chip logic analyzers. Also, increasingly the processor connects to external components that have a minimum speed, below which they will not operate. These speeds require the processor to operate faster than the external logic analyzer can accommodate.
As an alternative to sending data off-chip, attempts have been made to capture certain state data on chip, thereby reducing the problems of interfacing slower speed test equipment with high-speed devices. In the past, to the extent that designers sought to incorporate memory onto the chip for debug and test purposes, dedicated memory devices (usually RAM) were used. Thus, in prior art designs that attempted to capture debug and test information on-chip, a dedicated memory structure was incorporated into the chip design solely to store data for the debug and test modes. The problem with this approach, however, is that it requires the allocation of a significant amount of chip space to incorporate such dedicated memory devices, and these memory devices, while used extensively during the design and development phase of the chip, add little or nothing to the performance of the chip once it is released into production. Thus, the inclusion of dedicated memory space on the chip represents an opportunity cost, and means that functionality and/or performance is sacrificed to include this dedicated memory on the chip. Consequently, the inclusion of memory for debug purposes, while helpful in the debug and test phase, is generally viewed as undesirable because of the accompanying loss of performance and functionality that must be sacrificed. If a dedicated memory device is included on the chip, system designers normally require that such a memory be very small in size to minimize the cost increase (silicon cost is an exponential function of area, and memories are large structures), as well as the performance and functionality loss that accompanies the inclusion of such a dedicated memory. As the size of the dedicated memory becomes smaller, so too does the prospect that the state information stored in the dedicated memory will be sufficient to assist in the debug process. Thus, as the dedicated memory space becomes smaller, so too does the probability that useful debug data will be captured. In relative terms, the largest dedicated on-chip memories typically are incapable of storing very much data.
In assignee's co-pending application entitled Method And Apparatus For Efficiently Implementing Trace And/Or Logic Analysis Mechanisms On A Processor Chip, (Invention Disclosure P01–3848), the teachings of which are incorporated herein, the on-chip cache memory is used to store data from the on-chip logic analyzer. The use of the on-chip cache memory as a storage device for the on-chip logic analyzer permits the storage of a relatively large amount of state data on the chip as compared to previous designs. While the use of the on-chip cache memory greatly expands the amount of state data that can be stored on-chip, the extent of data that can be stored is not limitless. For a processor operating at 2 GHZ, the amount of data that can be stored in a 256 Kbyte cache represents only a few microseconds of data. Consequently, if the OCLA stores all incoming internal state data in the cache, the cache would quickly overflow, and potentially relevant data would be overwritten, or ignored.
External logic analyzers often include a word recognizer that functions a filter to select samples and/or operates as a trigger to start or stop acquisition. The word recognizer usually is implemented as a programmable logic device, which permits a system debugger to input state equations of interest, and the programmable logic device then compares incoming test data for matching state conditions. Internal state data occurring immediately after such a match can then be stored for later analysis. The ability to automatically monitor for certain conditions or events is beneficial because of the huge quantities of information that are generated by complex integrated circuits, and the high clock speeds of those devices. By the time that a user detects an interesting condition and presses a button, a processor may have generated gigabytes of data. The word recognizer thus provides a powerful tool for a system debugger because it permits a historical log to be generated almost instantaneously with the occurrence of a particular condition. More advanced word recognizers may provide selective masking of user-programmed values and counters and timers The ability to have such multi-level word recognizers and counter and timers is important for effective debug of complex logic, such as high-speed processors. Unfortunately, implementing a full-feature word recognizer and associated counters and timers has been viewed as unfeasible on the chip itself because of the large number of wires, logic devices and processing time that such devices would require. Thus, a full-feature word recognizer, capable of implementing arbitrary Boolean equations, typically is viewed as cost prohibitive to include on-chip. The absence of a full-feature word recognizer in existing on-chip logic analyzers makes it much more difficult to debug a design, thus introducing additional time and money to the development of new processors and complex integrated circuits. As an example, a system debugger may want to analyze state data being generated in the chip when certain combination of events occur—such as when a particular software instruction is executing (which can be determined by the address of the executing instructions), and when write transactions are occurring to a particular chip resource. If a device could be implemented that could examine internal state data, and only store state data on-chip when both conditions occur, then highly relevant state data would be available for the system debugger to use in analyzing and correcting the error.
It would be desirable if a system or technique was developed that would permit most of the useful features of a word recognizer to be included as part of an on-chip logic analyzer. It would also be advantageous if an economical, yet powerful, word recognizer could be developed that could be included on-chip without unduly raising the cost of the final product. Despite the apparent advantages such a design would offer, to date no such product has developed.